BS EN 60191-6-16:2007
Current
The latest, up-to-date edition.
Mechanical standardization of semiconductor devices Glossary of semiconductor tests and burn-in sockets for BGA, LGA, FBGA and FLGA
Hardcopy , PDF
English
31-07-2007
Foreword
1 Scope
2 Normative references
3 Terms and definitions
Annex ZA (normative) Normative references to international
publications with their corresponding European
publications
Presents a glossary of semiconductor sockets for BGA, LGA, FBGA and FLGA. This standard intends to establish definitions and unification of terminology relating to tests and burn-in sockets for BGA, LGA, FBGA and FLGA.
| Committee |
EPL/47
|
| DevelopmentNote |
Supersedes 05/30132036 DC. (07/2007)
|
| DocumentType |
Standard
|
| Pages |
14
|
| PublisherName |
British Standards Institution
|
| Status |
Current
|
| Supersedes |
IEC 60191-6-16:2007 gives a glossary of semiconductor sockets for BGA, LGA, FBGA and FLGA. This standard intends to establish definitions and unification of terminology relating to tests and burn-in sockets for BGA, LGA, FBGA and FLGA.
| Standards | Relationship |
| DIN EN 60191-6-16:2007-11 | Identical |
| EN 60191-6-16:2007 | Identical |
| IEC 60191-6-16:2007 | Identical |
| I.S. EN 60191-6-16:2007 | Identical |
| NF EN 60191-6-16 : 2013 | Identical |
| NBN EN 60191-6-16 : 2007 | Identical |
| UNE-EN 60191-6-16:2007 | Equivalent |
| IEC 60191-1:2007 | Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices |
| IEC 60191-2:2012 DB | Mechanical standardization of semiconductor devices - Part 2: Dimensions |
| EN 60191-3:1999 | Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits |
| IEC 60191-4:2013 | Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages |
| IEC 60191-3:1999 | Mechanical standardization of semiconductor devices - Part 3: General rules for the preparation of outline drawings of integrated circuits |
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