IEC 62530:2011
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
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SystemVerilog - Unified Hardware Design, Specification, and Verification Language
Hardcopy , PDF 1 User , PDF 3 Users , PDF 5 Users , PDF 9 Users
English
19-05-2011
26-07-2021
IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.
| Committee |
TC 91
|
| DevelopmentNote |
Stability Date: 2023. (09/2017)
|
| DocumentType |
Standard
|
| Pages |
1251
|
| PublisherName |
International Electrotechnical Committee
|
| Status |
Superseded
|
| SupersededBy | |
| Supersedes |
| Standards | Relationship |
| NEN IEC 62530 : 2011 | Identical |
| BS IEC 62530:2011 | Identical |
| BS IEC 62530:2007 | Identical |
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