IEEE 1364-2005

1 Overview
   1.1 Scope
   1.2 Conventions used in this standard
   1.3 Syntactic description
   1.4 Use of color in this standard
   1.5 Contents of this standard
   1.6 Deprecated clauses
   1.7 Header file listings
   1.8 Examples
   1.9 Prerequisites
2 Normative references
3 Lexical conventions
   3.1 Lexical tokens
   3.2 White space
   3.3 Comments
   3.4 Operators
   3.5 Numbers
   3.6 Strings
   3.7 Identifiers, keywords, and system names
   3.8 Attributes
4 Data types
   4.1 Value set
   4.2 Nets and variables
   4.3 Vectors
   4.4 Strengths
   4.5 Implicit declarations
   4.6 Net types
   4.7 Regs
   4.8 Integers, reals, times, and realtimes
   4.9 Arrays
   4.10 Parameters
   4.11 Name spaces
5 Expressions
   5.1 Operators
   5.2 Operands
   5.3 Minimum, typical, and maximum delay expressions
   5.4 Expression bit lengths
   5.5 Signed expressions
   5.6 Assignments and truncation
6 Assignments
   6.1 Continuous assignments
   6.2 Procedural assignments
7 Gate- and switch-level modeling
   7.1 Gate and switch declaration syntax
   7.2 and, nand, nor, or, xor, and xnor gates
   7.3 buf and not gates
   7.4 bufif1, bufif0, notif1, and notif0 gates
   7.5 MOS switches
   7.6 Bidirectional pass switches
   7.7 CMOS switches
   7.8 pullup and pulldown sources
   7.9 Logic strength modeling
   7.10 Strengths and values of combined signals
   7.11 Strength reduction by nonresistive devices
   7.12 Strength reduction by resistive devices
   7.13 Strengths of net types
   7.14 Gate and net delays
8 User-defined primitives (UDPs)
   8.1 UDP definition
   8.2 Combinational UDPs
   8.3 Level-sensitive sequential UDPs
   8.4 Edge-sensitive sequential UDPs
   8.5 Sequential UDP initialization
   8.6 UDP instances
   8.7 Mixing level-sensitive and edge-sensitive descriptions
   8.8 Level-sensitive dominance
9 Behavioral modeling
   9.1 Behavioral model overview
   9.2 Procedural assignments
   9.3 Procedural continuous assignments
   9.4 Conditional statement
   9.5 Case statement
   9.6 Looping statements
   9.7 Procedural timing controls
   9.8 Block statements
   9.9 Structured procedures
10 Tasks and functions
   10.1 Distinctions between tasks and functions
   10.2 Tasks and task enabling
   10.3 Disabling of named blocks and tasks
   10.4 Functions and function calling
11 Scheduling semantics
   11.1 Execution of a model
   11.2 Event simulation
   11.3 The stratified event queue
   11.4 Verilog simulation reference model
   11.5 Race conditions
   11.6 Scheduling implication of assignments
12 Hierarchical structures
   12.1 Modules
   12.2 Overriding module parameter values
   12.3 Ports
   12.4 Generate constructs
   12.5 Hierarchical names
   12.6 Upwards name referencing
   12.7 Scope rules
   12.8 Elaboration
13 Configuring the contents of a design
   13.1 Introduction
   13.2 Libraries
   13.3 Configurations
   13.4 Using libraries and configs
   13.5 Configuration examples
   13.6 Displaying library binding information
   13.7 Library mapping examples
14 Specify blocks
   14.1 Specify block declaration
   14.2 Module path declarations
   14.3 Assigning delays to module paths
   14.4 Mixing module path delays and distributed delays
   14.5 Driving wired logic
   14.6 Detailed control of pulse filtering behavior
15 Timing checks
   15.1 Overview
   15.2 Timing checks using a stability window
   15.3 Timing checks for clock and control signals
   15.4 Edge-control specifiers
   15.5 Notifiers: user-defined responses to timing violations
   15.6 Enabling timing checks with conditioned events
   15.7 Vector signals in timing checks
   15.8 Negative timing checks
16 Backannotation using the standard delay format (SDF)
   16.1 The SDF annotator
   16.2 Mapping of SDF constructs to Verilog
   16.3 Multiple annotations
   16.4 Multiple SDF files
   16.5 Pulse limit annotation
   16.6 SDF to Verilog delay value mapping
17 System tasks and functions
   17.1 Display system tasks
   17.2 File input-output system tasks and functions
   17.3 Timescale system tasks
   17.4 Simulation control system tasks
   17.5 Programmable logic array (PLA) modeling system tasks
   17.6 Stochastic analysis tasks
   17.7 Simulation time system functions
   17.8 Conversion functions
   17.9 Probabilistic distribution functions
   17.10 Command line input
   17.11 Math functions
18 Value change dump (VCD) files
   18.1 Creating four-state VCD file
   18.2 Format of four-state VCD file
   18.3 Creating extended VCD file
   18.4 Format of extended VCD file
19 Compiler directives
   19.1 `celldefine and `endcelldefine
   19.2 `default_nettype
   19.3 `define and `undef
   19.4 `ifdef, `else, `elsif, `endif, `ifndef
   19.5 `include
   19.6 `resetall
   19.7 `line
   19.8 `timescale
   19.9 `unconnected_drive and `nounconnected_drive
   19.10 `pragma
   19.11 `begin_keywords, `end_keywords
20 Programming language interface (PLI) overview
   20.1 PLI purpose and history
   20.2 User-defined system task/function names
   20.3 User-defined system task/function types
   20.4 Overriding built-in system task/function names
   20.5 User-supplied PLI applications
   20.6 PLI mechanism
   20.7 User-defined system task/function arguments
   20.8 PLI include files
21 PLI TF and ACC interface mechanism (deprecated)
22 Using ACC routines (deprecated)
23 ACC routine definitions (deprecated)
24 Using TF routines (deprecated)
25 TF routine definitions (deprecated)
26 Using Verilog procedural interface (VPI) routines
   26.1 VPI system tasks and functions
   26.2 VPI mechanism
   26.3 VPI object classifications
   26.4 List of VPI routines by functional category
   26.5 Key to data model diagrams
   26.6 Object data model diagrams
27 VPI routine definitions
   27.1 vpi_chk_error()
   27.2 vpi_compare_objects()
   27.3 vpi_control()
   27.4 vpi_flush()
   27.5 vpi_free_object()
   27.6 vpi_get()
   27.7 vpi_get_cb_info()
   27.8 vpi_get_data()
   27.9 vpi_get_delays()
   27.10 vpi_get_str()
   27.11 vpi_get_systf_info()
   27.12 vpi_get_time()
   27.13 vpi_get_userdata()
   27.14 vpi_get_value()
   27.15 vpi_get_vlog_info()
   27.16 vpi_handle()
   27.17 vpi_handle_by_index()
   27.18 vpi_handle_by_multi_index()
   27.19 vpi_handle_by_name()
   27.20 vpi_handle_multi()
   27.21 vpi_iterate()
   27.22 vpi_mcd_close()
   27.23 vpi_mcd_flush()
   27.24 vpi_mcd_name()
   27.25 vpi_mcd_open()
   27.26 vpi_mcd_printf()
   27.27 vpi_mcd_vprintf()
   27.28 vpi_printf()
   27.29 vpi_put_data()
   27.30 vpi_put_delays()
   27.31 vpi_put_userdata()
   27.32 vpi_put_value()
   27.33 vpi_register_cb()
   27.34 vpi_register_systf()
   27.35 vpi_remove_cb()
   27.36 vpi_scan()
   27.37 vpi_vprintf()
28 Protected envelopes
   28.1 General
   28.2 Processing protected envelopes
   28.3 Protect pragma directives
   28.4 Protect pragma keywords
Annex A (normative) Formal syntax definition
      A.1 Source text
      A.2 Declarations
      A.3 Primitive instances
      A.4 Module instantiation and generate construct
      A.5 UDP declaration and instantiation
      A.6 Behavioral statements
      A.7 Specify section
      A.8 Expressions
      A.9 General
Annex B (normative) List of keywords
Annex C (informative) System tasks and functions
      C.1 $countdrivers
      C.2 $getpattern
      C.3 $input
      C.4 $key and $nokey
      C.5 $list
      C.6 $log and $nolog
      C.7 $reset, $reset_count, and $reset_value
      C.8 $save, $restart, and $incsave
      C.9 $scale
      C.10 $scope
      C.11 $showscopes
      C.12 $showvars
      C.13 $sreadmemb and $sreadmemh
Annex D (informative) Compiler directives
      D.1 `default_decay_time
      D.2 `default_trireg_strength
      D.3 `delay_mode_distributed
      D.4 `delay_mode_path
      D.5 `delay_mode_unit
      D.6 `delay_mode_zero
Annex E (normative) acc_user.h (deprecated)
Annex F (normative) veriuser.h (deprecated)
Annex G (normative) vpi_user.h
Annex H (informative) Encryption/decryption flow
      H.1 Tool vendor secret key encryption system
      H.2 IP author secret key encryption system
      H.3 Digital envelopes
Annex I (informative) Bibliography
Index

Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001.