JEDEC JESD 65B : 2003
Current
Current
The latest, up-to-date edition.
Definition of Skew Specifications for Standard Logic Devices
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
01-09-2003
Publisher
Free
Including GST where applicable
This standard defines skew specifications and skew testing for standard logic devices.
| DocumentType |
Standard
|
| Pages |
19
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Current
|
| Supersedes |
| DSCC 15212C:2025 | MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 2M x 32-BIT (64M), RADIATION-HARDENED, PIPELINED, SYNCHRONOUS SRAM (SSRAM), MONOLITHIC SILICON |
Summarise
Free
Including GST where applicable
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