HD 524 : 200S1

Describes a high performance backplane bus for use in microprocessor based systems. This parallel bus supports single and block transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaken protocol. The bus allocation provides for multiprocessor architectures. This bus also supports inter-module interrupts for facilitating quick response to internal and external events. The mechanics of the boards and chassis are based on IEC Publication 297: Dimension of Panels and Racks. Note. - This bus is similar to the VME bus.