I.S. HD 524:S1 1990

Describes a high performance back-plane bus for use in microprocessor based systems. The parallel bus supports single and block transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaking protocol. The bus allocation provides for multiprocessor architectures. This bus also supports inter-module interrupts for facilitating quick response to internal and external events. The mechanics of the boards and chassis are based on HD 493: Dimensions of Panels and Racks.