IEEE 1076.4-2000
Withdrawn
IEEE Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification
English
09-28-2001
01-26-2009
FOREWORD
IEEE Introduction
1. Overview
2. References
3. Basic elements of the VITAL ASIC modeling specification
4. The Level 0 specification
5. Backannotation
6. The Level 1 specification
7. Predefined primitives and tables
8. Timing constraints
9. Delay selection
10. The Level 1 Memory specification
11. VITAL Memory function specification
12. VITAL memory timing specification
13. The VITAL standard packages
Annex A (informative) - Syntax summary
Annex D (informative) - List of Participants
Annex B (informative) - Glossary
Annex C (informative) - Bibliography
Pertains at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs.
| Committee |
Design Automation
|
| DevelopmentNote |
Also numbered as IEC 61691-5. (10/2004) Supersedes IEEE DRAFT 1076.4 (02/2005)
|
| DocumentType |
Standard
|
| Pages |
448
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Withdrawn
|
| Supersedes |
| IEEE 1076-2008 REDLINE | IEEE Standard VHDL Language Reference Manual |
| BS IEC 61691-1-1:2011 | Behavioural languages VHDL Language reference manual |
| IEC 61691-1-1:2011 | Behavioural languages - Part 1-1: VHDL Language Reference Manual |
| PD R217-020:2002 | Electronic system specification languages. VHDL modelling guidelines |
| SAE J2546_200202 | Model Specification Process Standard |
| IEEE 1164-1993 | IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) |
| IEEE 1076-2008 REDLINE | IEEE Standard VHDL Language Reference Manual |
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