IEEE/IEC 62530-2-2023
Current
IEEE/IEC International Standard--SystemVerilog--Part 2: Universal Verification Methodology Language Reference Manual
Hardcopy , PDF
English
10-19-2023
This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments.
| DocumentType |
Standard
|
| ISBN |
979-8-8557-0213-2
|
| Pages |
461
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Current
|
| IEEE 1800-2017 | IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language |
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