JEDEC JEP 158:2009
Superseded
Superseded
View Superseded by
3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
11-01-2009
Publisher
Superseded date
03-27-2026
Superseded by
Free
Excluding Tax where applicable
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests.
| DocumentType |
Standard
|
| Pages |
24
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Superseded
|
| SupersededBy |
| JEDEC JESD93A:2022 | MULTICHIP MODULES (MCM) |
Summarise
Free
Excluding Tax where applicable
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