JEDEC JESD 51-3:1996
Current
Current
LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES:
Published date
08-01-1996
Publisher
Sorry this product is not available in your region.
This standard describes design requirements for a single layer, leaded surface mount integrated circuit package thermal test board.
| DocumentType |
Standard
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Current
|
| DSCC V62/09629B:2023 | MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON |
| DSCC V62/13628 : A | MICROCIRCUIT, DIGITAL, MIXED SIGNAL MICRCONTROLLER, MONOLITHIC SILICON |
| DSCC V62/13628B:2025 | MICROCIRCUIT, DIGITAL, MIXED SIGNAL MICRCONTROLLER, MONOLITHIC SILICON |
Summarise
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