JEDEC JESD47K:2018
Superseded
Superseded
View Superseded by
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
08-01-2018
Publisher
Superseded date
12-23-2022
Superseded by
US$95.00
Excluding Tax where applicable
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.
| DocumentType |
Standard
|
| Pages |
34
|
| ProductNote |
This standard also refer to JP-001,JS-001,JS-002
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Superseded
|
| SupersededBy | |
| Supersedes |
Summarise
US$95.00
Excluding Tax where applicable