NEN IEC 62142 : 2005
Withdrawn
Withdrawn
VERILOG REGISTER TRANSFER LEVEL SYNTHESIS
Published date
01-12-2013
Publisher
Withdrawn date
12-03-2010
Sorry this product is not available in your region.
Defines a set of modeling rules for writing Verilog[R] HDL descriptions for synthesis. It defines how the semantics of Verilog HDL are used, for example, to describe level- and edge-sensitive logic. It also explains the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
| DocumentType |
Standard
|
| PublisherName |
Netherlands Standards
|
| Status |
Withdrawn
|
| Standards | Relationship |
| IEC 62142:2005 | Identical |
Summarise
Sorry this product is not available in your region.