IEC 60191-6-3:2000
Current
The latest, up-to-date edition.
Mechanical standardization of semiconductor devices - Part 6-3: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Measuring methods for package dimensions of quad flat packs (QFP)
Hardcopy , PDF 1 User , PDF 3 Users , PDF 5 Users , PDF 9 Users
English, English - French
29-09-2000
FOREWORD
1 Scope
2 Normative references
3 Definitions
4 Measuring methods
IEC 60191-6-3:2000 stipulates a method for quad flat packs (QFP) measuring dimensions which are classified into Form E.
| Committee |
TC 47/SC 47D
|
| DevelopmentNote |
Also numbered as BS EN 60191-6.3 (09/2005) A Bilingual edition has been published. (01/2013) Stability Date: 2020. (09/2017)
|
| DocumentType |
Standard
|
| Pages |
17
|
| PublisherName |
International Electrotechnical Committee
|
| Status |
Current
|
| Standards | Relationship |
| NEN EN IEC 60191-6-3 : 2001 | Identical |
| I.S. EN 60191-6-3:2001 | Identical |
| PN EN 60191-6-3 : 2002 | Identical |
| CEI EN 60191-6-3 : 2001 | Identical |
| EN 60191-6-3:2000 | Identical |
| DIN EN 60191-6-3:2001-06 | Identical |
| NF EN 60191-6-3 : 2001 | Identical |
| UNE-EN 60191-6-3:2000 | Identical |
| EN IEC 60191-1:2018 | Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices |
| IEC 60191-6-6:2001 | Mechanical standardization of semiconductor devices - Part 6-6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine pitch land grid array (FLGA) |
| IEC 60191-1:2018 | Mechanical standardization of semiconductor devices - Part 1: General rules for the preparation of outline drawings of discrete devices |
| I.S. EN IEC 60191-1:2018 | MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 1: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF DISCRETE DEVICES |
| IEC 60191-6:2009 | Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages |
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