BS EN 61523-2:2002
Withdrawn
Delay and power calculation standards Pre-layout delay calculation specification for CMOS ASIC libraries
Hardcopy , PDF
English
09-27-2002
08-31-2014
| Committee |
EPL/501
|
| DocumentType |
Standard
|
| Pages |
42
|
| PublisherName |
British Standards Institution
|
| Status |
Withdrawn
|
Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.
| Standards | Relationship |
| DIN EN 61523-2:2003-06 | Identical |
| NF EN 61523-2 : 2003 | Identical |
| EN 61523-2:2002 | Identical |
| I.S. EN 61523-2:2002 | Identical |
| NBN EN 61523-2 : 2003 | Identical |
| IEC 61523-2:2002 | Identical |
| UNE-EN 61523-2:2002 | Equivalent |
| IEEE 1481-2009 | IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA) |
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