IEC 61523-2:2002
Withdrawn
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
Hardcopy , PDF
English
05-17-2002
12-31-2021
Foreword
1 Scope and object
2 Normative references
3 Relations with other companion standards activities
4 Terms and definitions
5 Pre-layout delay calculation method for CMOS ASIC
libraries
Annex A (informative) Four points interpolation
Annex B (informative) Three points interpolation
Annex C (informative) Selection method of interpolation
plane
Annex D (informative) Theoretical accuracy comparison
between two interpolation methods
Annex E (informative) Application example
Annex F (informative) Example of Cn, Ts, Tpd tables by
delay calculation language
Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.
| DocumentType |
Standard
|
| Pages |
38
|
| PublisherName |
International Electrotechnical Committee
|
| Status |
Withdrawn
|
| Standards | Relationship |
| NEN EN IEC 61523-2 : 2002 | Identical |
| I.S. EN 61523-2:2002 | Identical |
| PN EN 61523-2 : 2004 | Identical |
| BS EN 61523-2:2002 | Identical |
| EN 61523-2:2002 | Identical |
| NF EN 61523-2 : 2003 | Identical |
| DIN EN 61523-2:2003-06 | Identical |
| UNE-EN 61523-2:2002 | Identical |
| IEEE 1481-2009 | IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA) |
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