MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-20: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGES - MEASURING METHODS FOR PACKAGE DIMENSIONS OF SMALL OUTLINE J-LEAD PACKAGES (SOJ)

Available format(s)

Hardcopy , PDF

Language(s)

English

Published date

01-01-2011

Publisher

Comitato Elettrotecnico Italiano

FOREWORD
1. Scope
2. Normative references
3. Terms and definitions
4. Measuring methods
Annex ZA (normative) - Normative references
to international publications with their
corresponding European publications

Describes the methods to measure package dimensions of small outline J-lead-packages (SOJ), package outline form E in accordance with IEC 60191-4.

Committee	CT 309
DevelopmentNote	Classificazione CEI 47-78. (12/2011)
DocumentType	Standard
Pages	18
PublisherName	Comitato Elettrotecnico Italiano
Status	Current

Standards	Relationship
EN 60191-6-20:2010	Identical
IEC 60191-6-20:2010	Identical

IEC 60191-6:2009	Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
IEC 60191-4:2013	Mechanical standardization of semiconductor devices - Part 4: Coding system and classification into forms of package outlines for semiconductor device packages
EN 60191-6:2009	Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

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CEI EN 60191-6-20 : 2011

MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES - PART 6-20: GENERAL RULES FOR THE PREPARATION OF OUTLINE DRAWINGS OF SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGES - MEASURING METHODS FOR PACKAGE DIMENSIONS OF SMALL OUTLINE J-LEAD PACKAGES (SOJ)

Table of Contents

Abstract

General Product Information

International Equivalents

Standards Referencing This Book

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