EN 61691-3-3:2001
Withdrawn
Behavioural languages - Part 3-3: Synthesis in VHDL
12-14-2001
09-01-2004
Foreword
INTRODUCTION
1 Overview
2 References
3 Definitions
4 Interpretation of the standard logic types
5 The STD_MATCH function
6 Signal edge detection
7 Standard arithmetic packages
Annex A (informative) Notes on the package functions
This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.
| Committee |
CLC/SR 91
|
| DocumentType |
Standard
|
| PublisherName |
European Committee for Standards - Electrical
|
| Status |
Withdrawn
|
| Standards | Relationship |
| PN EN 61691-3-3 : 2004 | Identical |
| IEC 61691-3-3:2001 | Identical |
| DIN EN 61691-3-3:2002-11 | Identical |
| NEN EN IEC 61691-3-3 : 2002 | Identical |
| I.S. EN 61691-3-3:2002 | Identical |
| NF EN 61691-3-3 : 2002 | Identical |
| NBN EN 61691 3-3 : 2002 | Identical |
| BS EN 61691-3-3:2002 | Identical |
| UNE-EN 61691-3-3:2001 | Identical |
| IEEE 1164-1993 | IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) |
| IEEE 1076-2008 REDLINE | IEEE Standard VHDL Language Reference Manual |