IEC 61691-3-3:2001

FOREWORD
INTRODUCTION
1. Overview
   1.1 Scope
   1.2 Terminology
   1.3 Conventions
2. References
3. Definitions
4. Interpretation of the standard logic types
   4.1 The STD_LOGIC_1164 values
   4.2 Static constant values
   4.3 Interpretation of logic values
5. The STD_MATCH function
6. Signal edge detection
7. Standard arithmetic packages
   7.1 Allowable modifications
   7.2 Compatibility with IEEE Std 1076-1987
   7.3 The package texts
Annex A (informative) Notes on the package functions
      A.1 General considerations
          A.1.1 Mixing SIGNED and UNSIGNED operands
          A.1.2 Mixing vector and element operands
      A.2 Arithmetic operator functions
          A.2.1 Overflow of maximum negative value
          A.2.2 Lack of carry and borrow
          A.2.3 Return value for metalogical and
                high-impedance operands
      A.3 Relational operator functions
          A.3.1 Justification of vector operands
          A.3.2 Expansion of vector operands compared to
                integers
          A.3.3 Return value for metalogical and
                high-impedance operands
      A.4 Shift functions
          A.4.1 Multiplication by a power of 2 with remaindering
          A.4.2 Division by a power of 2
      A.5 Type conversion functions
          A.5.1 Overflow in conversion to INTEGER
          A.5.2 Conversion between SIGNED and UNSIGNED
      A.6 Logical operator functions
          A.6.1 Application to SIGNED and UNSIGNED
          A.6.2 Index range of return values
      A.7 The STD_MATCH function

This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.