IEC 60191-3:1999

Foreword
1 General
2 Terminology and definitions
3 Cross-referencing of packages
4 Terminal identification - Numbering of terminals
5 Dimensions and reference letter symbols
6 Drawing layout
7 Dimensioning and tolerances
8 Inter-conversion of inch and millimetre dimensions,
      and rules for rounding-off
9 Definition of families
10 Examples of drawings
11 Design procedure for dimensions of integrated circuit
      packages
12 Rules for mounting integrated circuit packages into
      carriers
13 Bending of terminals of QUIL packages
14 Pin grid arrays
15 Rule for orientation of integrated circuit packages in
      handling and shipping carriers such as stick magazines
      and rails
Annex A (normative) Limits applicable for the dimensions of
                    integrated circuit package outlines
Annex B (informative) Example drawings showing cross-
                      referencing of packages, utilization
                      of reference letter symbols, terminal
                      identification and index area
Annex C (normative) Terminal identification and numbering of
                    terminals of devices with terminals
                    disposed in three or more rows in each
                    orthogonal direction
Annex D (normative) Recommended dimensions of integrated
                    circuit packages of Form G family
Annex E (normative) General rules for the preparation of
                    outline drawings of packages of Form G
                    intended for automated handling
Annex F (normative) General rules for the preparation of
                    outline drawings of pin grid arrays
Annex G (normative) Rule for orientation of integrated
                    circuit packages in handling and shipping
                    carriers such as stick magazines and rails
Annex G (normative) Rule for orientation of integrated circuit
                    packages in handling and shipping carriers
                    such as stick magazines and rails
Annex H (normative) Bottom view method for Terminal No 1
                    recognition
Annex K (normative) Gate burrs, mold flash and protrusions

Gives guidance on the preparation of drawings of integrated circuits outlines.