IEC PAS 62181:2000

1 Scope
      1.1 Purpose
      1.2 Classification
      1.3 Level
2 Definitions
      2.1 Cool-down time
      2.2 DUT
      2.3 GND (Ground)
      2.4 Input pins
      2.5 I/O (Bi-directional) pins
      2.6 Isupply
      2.7 I-test
      2.8 Latch-up
      2.9 Logic-high
      2.10 Logic-low
      2.11 Maximum Vsupply
      2.12 "No Connect" pin
      2.13 Nominal Isupply (Inom)
      2.14 Output pin
      2.15 Preconditioned pin
      2.16 Testing of dynamic devices
      2.17 Test condition
      2.18 Timing related input pin
      2.19 Trigger Pulse
      2.20 Trigger duration
      2.21 Vsupply pin (or pin group)
      2.22 Vsupply overvoltage test
3 Apparatus and Material
      3.1 Latch-up tester
      3.2 Automated test equipment (ATE)
      3.3 Heat Source
4 Procedure
      4.1 General latch-up test procedure
      4.2 Detailed latch-up test procedure
             4.2.1 I-test
             4.2.2 Vsupply overvoltage test
             4.2.3 Testing dynamic devices
             4.2.4 DUT disposition
             4.2.5 Record keeping
5 Failure Criteria
6 Summary
Table 1 - Test Matrix [7]
Table 2 - Timing specifications for I-test and vsupply
          overvoltage test
Figure 1 - Latch-up test flow
Figure 2 - Test waveform for positive I-test
Figure 3 - Test waveform for negative I-test
Figure 4 - Test waveform for Vsupply overvoltage test
Figure 5 - The equivalent circuit for positive input/output
           I-test latch-up testing
Figure 6 - The equivalent circuit for negative input/output
           I-test latch-up testing
Figure 7 - The equivalent circuit for Vsupply overvoltage
           test latch-up testing

Establishes a method for determining IC latch-up characteristics and to define latch-up failure criteria. Applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies.