JEDEC JESD 204:2017
Superseded
Superseded
View Superseded by
SERIAL INTERFACE FOR DATA CONVERTERS
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
11-21-2018
Publisher
Superseded date
01-21-2023
Superseded by
Excluding Tax where applicable
This standard describes a serialized interface between data converters and logic devices.
| DocumentType |
Standard
|
| Pages |
0
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Superseded
|
| SupersededBy |
| DSCC V62/22611:2022 | MICROCIRCUIT, DIGITAL-LINEAR, 12 BIT, RF SAMPLING ANALOG TO DIGITAL CONVERTER MONOLITHIC SILICON |
| DSCC 18209B:2021 | MICROCIRCUIT, DIGITAL-LINEAR, 12 BIT, RF SAMPLING, ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON |
| DSCC 18209C:2025 | MICROCIRCUIT, DIGITAL-LINEAR, 12 BIT, RF SAMPLING, ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON |
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