JEDEC JESD22-B113C:2025
Current
Current
Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of SMT ICs for Handheld Electronic Products
Available format(s)
Hardcopy , PDF
Language(s)
English
Published date
11-01-2025
Publisher
Free
Excluding Tax where applicable
The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of SMT ICs in an accelerated test environment for handheld electronic products applications.
| DocumentType |
Test Method
|
| Pages |
24
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Current
|
| Supersedes |
Summarise
Free
Excluding Tax where applicable