JEDEC JESD403-1B:2022
Superseded
View Superseded by
JEDEC Module Sideband Bus(SidebandBus)
Hardcopy , PDF
English
08-01-2022
12-19-2023
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages.
| DocumentType |
Standard
|
| Pages |
58
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Superseded
|
| SupersededBy | |
| Supersedes |
| JEDEC JESD82-531A:2024 | DDR5 Clock Driver Definition (DDR5CK01) |
Please Login or Create an Account so you can add users to your Multi user PDF Later.
Important note : All end users must be registered with an Account prior to user licenses being assigned.
Users cannot be edited or removed once added to your Multi user PDF.