JEDEC JESD82-531A:2024
Superseded
View Superseded by
DDR5 Clock Driver Definition (DDR5CK01)
Hardcopy , PDF
English
01-01-2024
01-20-2026
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications.
| DocumentType |
Standard
|
| Pages |
114
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Superseded
|
| SupersededBy | |
| Supersedes |
| JEDEC JESD 8-11A.01:2007 | ADDENDUM No. 11A.01 to JESD8 - 1.5 V +/- 0.1 V (NORMAL RANGE) AND 0.9 - 1.6 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS |
| JEDEC JESD79-5B:2022 | DDR5 SDRAM |
| JEDEC JESD403-1B:2022 | JEDEC Module Sideband Bus(SidebandBus) |
| ANSI/ESDA/JEDEC JS-001:2017 | ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing - Human Body Model (HBM) - Component Level<br> |
| JEDEC JEP 104:1983 | REFERENCE GUIDE TO LETTER SYMBOLS FOR SEMICONDUCTOR DEVICES |
| ANSI/ESDA/JEDEC JS-002 : 2018 | ANSI/ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL<br> |
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