DSCC 93141D:2025
Current
Current
The latest, up-to-date edition.
MICROCIRCUIT, DIGITAL, ADVANCED CMOS, 9-BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER, NON-INVERTING THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON
Published date
27-05-2025
Publisher
Sorry this product is not available in your region.
This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V).
| DocumentType |
Revision
|
| PublisherName |
Defense Supply Centre Columbus
|
| Status |
Current
|
| Supersedes |
| JEDEC JESD 78:1997 | IC LATCH-UP TEST |
| MIL-STD-883 Revision K:2016 | Microcircuits |
| JEDEC JESD 20:1990 | STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES: |
| MIL-HDBK-780 Revision D:2004 | Standard Microcircuit Drawings |
| MIL-PRF-38535 Revision L:2018 | Integrated Circuits (Microcircuits) Manufacturing, General Specification for |
| MIL-STD-1835 Revision D:2004 | Electronic Component Case Outlines |
Summarise
Sorry this product is not available in your region.