IEEE 1364-2001
Superseded
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
View Superseded by
IEEE Standard Verilog Hardware Description Language
Amended by
Available format(s)
PDF
Published date
28-09-2001
Superseded date
11-12-2009
Superseded by
£126.30
Excluding VAT
| Committee |
Design Automation
|
| DocumentType |
Standard
|
| Pages |
815
|
| ProductNote |
New Child ERR 1 Is Now Added
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Superseded
|
| SupersededBy | |
| Supersedes |
| IEEE 1800-2012 | IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language |
| IEEE/IEC 61691-7-2009 | Behavioural languages - Part 7: SystemC Language Reference Manual |
| IEEE/IEC 62142-2005 | IEC/IEEE International Standard - Verilog(R) Register Transfer Level Synthesis |
| IEEE 1666-2005 | IEEE Standard SystemC(R) Language Reference Manual |
| IEEE 1800-2009 REDLINE | IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language |
| IEEE/IEC 62530-2011 | IEEE/IEC International Standard - SystemVerilog -- Unified Hardware Design, Specification, and Verification Language |
Summarise
£126.30
Excluding VAT
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