IPC 2141 : A:2004

1 SCOPE
2 APPLICABLE DOCUMENTS
   2.1 IPC
3 ENGINEERING DESIGN OVERVIEW
   3.1 Device Selection
   3.2 Interconnection
   3.3 Printed Board and Printed Board Assemblies
   3.4 Performance Requirements
4 DESIGN OF CONTROLLED IMPEDANCE CIRCUITS
   4.1 Unbalanced Line Configurations
   4.2 Unbalanced Line Equations
   4.3 Balanced Line Configuration
   4.4 Balanced Line Equations
   4.5 Controlled Impedance Design Rules
   4.6 Crosstalk Guidelines
   4.7 Design Guidelines for Controlled
       Impedance Test Structures
   4.8 Decoupling/Capacitor Guidelines
   4.9 EMI Considerations in Design Layout
5 DESIGN FOR MANUFACTURING
   5.1 Process Rules in CAD
   5.2 Design Complexity and Correlation to Cost
6 DATA DESCRIPTION
   6.1 Details of Construction
   6.2 Isolation of Data by Net Class (Noise,
       Timing, Capacitance, and Impedance)
   6.3 Electrical Performance
7 MATERIALS
   7.1 Resin Systems
   7.2 Reinforcements
   7.3 Prepregs, Bonding Layers and Adhesives
   7.4 Frequency Dependence
8 FABRICATION
   8.1 General
   8.2 Preproduction Processes
   8.3 Production Processes
   8.4 Impact of Defects at High Frequencies
   8.5 Data Description
9 TIME DOMAIN REFLECTOMETRY TESTING
   9.1 Description of Time-Domain Reflectometry
   9.2 Uses of TDR
   9.3 TDR System Description
   9.4 TDR Operation
   9.5 Test Structure
   9.6 TDR Calibration
   9.7 Alternative TDR Design
Figures
Tables

Presents expanded data for logic families, updated equations for unbalanced lines, new equations for balanced line configurations, and detailed comparisons between capacitive lines and transmission lines, including propagation within transmission lines.