JEDEC JESD 8-15A : 2003
Current
The latest, up-to-date edition.
STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18)
Hardcopy , PDF
English
01-09-2003
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V.
| DocumentType |
Revision
|
| Pages |
22
|
| PublisherName |
JEDEC Solid State Technology Association
|
| Status |
Current
|
| Supersedes |
| JEDEC JESD82-17.01:2023 | Definition of the SSTUA32S868 and SSTUA32D868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications |
| JEDEC JESD82-27.01:2023 | Definition of the SSTUB32869 Registered Applications Buffer with Parity for DDR2 RDIMM |
| DSCC 16208H:2024 | MICROCIRCUIT, MEMORY, DIGITAL, CMOS, LOW POWER REPROGRAMMABLE 151,824 LOGIC ELEMENT FLASH FIELD PROGRAMMABLE GATE ARRAY WITH DECOUPLING CAPACITORS,MONOLITHIC SILICON |
| JEDEC JESD82-14A.01:2021 | Definition of the SSTUB32868 1.8 V (Minor Editorial Revision of JESD82-14A, October 2006) Configurable Registered Buffer with Parity for DDR2 RDIMM Applications |
Please Login or Create an Account so you can add users to your Multi user PDF Later.
Important note : All end users must be registered with an Account prior to user licenses being assigned.
Users cannot be edited or removed once added to your Multi user PDF.