JEDEC JESD22-A117C:2011

The following details shall be specified in the applicable device specification and/or the supplier's internal
stress test specification, along with the rationale

This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated
circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes withoutfailure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention).
This Standard specifies the procedural requirements for performing valid endurance and retention tests
based on a qualification specification. Endurance and retention qualification specifications (for cycle
counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using
knowledge-based methods as in JESD94.This stress test does not replace other stress test qualification requirements. The program/erase endurance
and data retention test for qualification and monitoring, using the parameter levels specified in JESD47, is
considered destructive. Lesser test parameter levels (e.g., of temperature, number of cycles, retention
bake duration) may be used for screening as long as these parameter levels have been verified by the
device manufacturer to be nondestructive; this can be performed anywhere from wafer level to finished
device.