EN 60191-6-17:2011
Current
Current
The latest, up-to-date edition.
Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA)
Published date
15-04-2011
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FOREWORD
INTRODUCTION
1 Scope
2 Normative references
3 Definitions
4 Terminal position numbering
5 Drawings
6 Dimensions
7 Dimension table
Annex ZA (normative) - Normative references to
international publications with their
corresponding European publications
IEC 60191-6-17:2011 provides outline drawings and dimensions for stacked packages and individual stackable packages in the form of FBGA or FLGA.
| Committee |
CLC/TC 47X
|
| DocumentType |
Standard
|
| PublisherName |
European Committee for Standards - Electrical
|
| Status |
Current
|
| Standards | Relationship |
| IEC 60191-6-17:2011 | Identical |
| DIN EN 60191-6-17:2011-09 | Identical |
| NF EN 60191-6-17 : 2012 | Identical |
| BS EN 60191-6-17:2011 | Identical |
| NEN EN IEC 60191-6-17 : 2011 | Identical |
| NBN EN 60191-6-17 : 2011 | Identical |
| I.S. EN 60191-6-17:2011 | Identical |
| PN EN 60191-6-17 : 2011 | Identical |
| CEI EN 60191-6-17 : 2012 | Identical |
| UNE-EN 60191-6-17:2011 | Identical |
| IEC 60191-6:2009 | Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages |
| IEC 60191-6-5:2001 | Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA) |
| EN 60191-6:2009 | Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages |
| EN 60191-6-5:2001 | Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA) |
Summarise
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