IEC 63011-1:2018
Current
The latest, up-to-date edition.
Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
Hardcopy , PDF
English, English - French
28-11-2018
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
| Committee |
TC 47/SC 47A
|
| DocumentType |
Standard
|
| ISBN |
978-2-8322-6290-0
|
| Pages |
0
|
| ProductNote |
THIS STANDARD ALSO REFERS TO IEC 63011-3
|
| PublisherName |
International Electrotechnical Committee
|
| Status |
Current
|
| Standards | Relationship |
| BS IEC 63011-1:2018 | Identical |
| BS EN 61362:2012 | Identical |
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